Computers designing themselves: AI could speed up computer chip design

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Artificial intelligence (AI) could be used to design computer chips more efficiently than human engineers, according to researchers at Google who created a ‘floorplanning’ program to help with chip design. Designing the physical layout of a computer chip (‘floorplanning’) is a complex and time-consuming task, but essential in determining overall chip performance. The team developed a series of algorithms that treated chip floorplanning as a game, and the most efficient design ‘won’. In under six hours, the method developed chips that were similar or more efficient than those designed by human experts. The researchers say this could potentially save thousands of hours of human effort for each new generation of computer chip, and this method is already being used to develop the next generation of Google’s AI computer systems.

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From: Springer Nature

Computer chip design can be greatly accelerated by using machine learning tools, according to a paper in Nature this week. The approach is shown to generate viable chip designs that perform at least as well as those produced by human engineers, but with the design process taking hours rather than months. This method is already being used in the design of the next generation of Google’s artificial intelligence computer systems.

The placement of different components on a computer chip is key to determining overall chip performance. Designing the physical layout of a computer chip is a complex and time-consuming task that has been difficult to automate, requiring intense efforts by expert human design engineers. Machine learning tools can be used to accelerate this so-called floorplanning process, Azalia Mirhoseini, Anna Goldie and colleagues demonstrate.

The authors pose chip floorplanning as a reinforcement learning problem and develop a neural network that can generate viable chip designs. They train a reinforcement learning agent to treat floorplanning as a game, in which the components are ‘pieces’, the canvas on which components sit is the ‘board’ and the ‘winning result’ is optimal performance according to a range of evaluation metrics (based on a reference dataset of 10,000 chip placements). The method can generate viable chip floorplans that are comparable or superior to those designed by human experts in under six hours, potentially saving thousands of hours of human effort for each new generation of computer chips, the authors note.

“The development of methods for automated chip design that are better, faster and cheaper than current approaches will help to keep alive the ‘Moore’s law’ trajectory of chip technology,” (in which the number of components per chip has roughly doubled every two years) writes Andrew Kahng in an accompanying News & Views article. He adds that the revelation that the authors’ floorplan solutions are being used in the design of Google’s next-generation AI processors demonstrates that the designs are good enough to be manufactured on a large scale.

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Organisation/s: Google Research, USA
Funder: This project was a collaboration between Google Brain and the Google Chip Implementation and Infrastructure (CI2) Team. We thank M. Bellemare, C. Young, E. Chi, C. Stratakos, S. Roy, A. Yazdanbakhsh, N. Myung-Chul Kim, S. Agarwal, B. Li, S. Bae, A. Babu, M. Abadi, A. Salek, S. Bengio and D. Patterson for their help and support.
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